1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor device module and a method of manufacturing the semiconductor device.
2. Related Art
In accordance with the ongoing reduction in dimensions and weight of electronic devices, demand for micronization of the electronic components to be employed is continuously increasing. On the other hand, the demand for higher performance, such as a high speed operation and larger memory capacity, has also been increasing. Accordingly, an SiP (System in Package) in which a plurality of semiconductor chips electrically connected to one another is integrated has been developed, as a method for system integration at the device level that can satisfy both of the micronization in dimensions and higher performance.
A primary part of the SiP technique is a Chip-On-Chip combination technique, which includes disposing so as to oppose each main face of devices having a different optimum designing parameter in a wafer process, such as a CMOS logic and a DRAM, or devices that are difficult to integrate in a wafer process, such as a silicon device and a compound semiconductor device, and electrically connecting the devices via bump electrodes in a shortest distance. Such a Chip-On-Chip technique is expected to achieve a SiP that offers a higher performance and a higher operation speed.
However, some issues to be addressed have already been discovered in such a technique, such as deterioration in strength of each individual bump due to a reduction in size, or difficulty in injecting a sealing resin required for protection from an external environment, which are supposed to come up when still further micronization and improvement in performance are required in future and the bump electrode are compelled to be made smaller.
Therefore, a related art such as JP-A No. 2002-26238 proposes employing a bump for preventing a chip from bending backward, to thereby protect an electrode bump formed according to the chip-on-chip technique. In JP-A No. 2002-26238, an upper chip includes upper bumps arranged along a periphery region of an interconnect forming surface, and a lower chip has lower bumps located at positions corresponding to the upper bumps.
In addition, the lower chip and the upper chip both include, apart from the lower bumps and the upper bumps, a reaction force blocking lower bump and a reaction force blocking upper bump respectively, designed to sustain a reaction force generated by the chip in a direction of bending backward, located at a central portion of the chip or inside the periphery region thereof. When stacking the lower bumps and the upper bumps so as to put the bumps in contact, the reaction force blocking lower bump and the reaction force blocking upper bump are also put into mutual contact.